Some computer systems employ multiple processors. These processors may, for example, be used to process information received from a remote computer via a network. Typically, the information is received at the computer by one or more network interface controllers (NICs) that receive information transmitted in accordance with a prescribed network communication protocol (e.g., TCP, or Transmission Control Protocol). The received information may, for example, include requests to perform networking-related operations that may be distributed across the multiple processors for execution. Allowing multiple processors to simultaneously perform networking-related operations can improve the computer's performance. One known architecture which employs multiple processors to perform networking-related operations is a “symmetric multiprocessor” (SMP) system architecture.
In a conventional technique for processing information received via a network on an SMP system, a NIC on the computer receives a data packet and stores it in memory with a packet descriptor that includes pointer information identifying the location of the data in memory. If a previous packet is not currently being processed, an interrupt is generated to one of the processors, and an interrupt service routine (ISR) executes, suspending further interrupts from the NIC while a deferred procedure call (DPC) is requested to run on a processor selected to handle the packet. As the DPC executes, one or more data packets and descriptors are retrieved from memory to build an array, and the processor then initiates processing the packet. After the DPC completes, further interrupts from the NIC are re-enabled, so that additional packets may be distributed to one or more other of the processors.
In some conventional multi-processor architectures, one or more processors may have associated memory. For example, in a Non-Uniform Memory Access (NUMA) system, one or more processors may comprise a NUMA node having an associated set of memory addresses that are accessed most efficiently by processors in the NUMA node. In this respect, a particular NUMA node on a system may be thought of as being “closest” to the set of memory addresses associated with the node, and “further away” from other sets of memory addresses that are each associated with other NUMA nodes on the system. In a NUMA-enabled system, access by a first NUMA node to a memory address associated with a second NUMA node is slower than access by the second NUMA node would be.